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An FPGA-Based Acceleration Methodology and Performance Model for Iterative Stencils.

, , , и . IPDPS Workshops, стр. 115-122. IEEE Computer Society, (2018)

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Enrico Fest

Enrico Körner

Enrico Meier

Enrico Streit

Enrico Schramm

 

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Performance Portable FPGA Design., , , , , , , и . FPGA, стр. 324. ACM, (2020)Adaptable Register File Organization for Vector Processors., , , , , , , , и . CoRR, (2021)Adaptable Register File Organization for Vector Processors., , , , , , , , и . HPCA, стр. 786-799. IEEE, (2022)DVINO: A RISC-V Vector Processor Implemented in 65nm Technology., , , , , , , , , и 33 other автор(ы). DCIS, стр. 1-6. IEEE, (2022)Pearson Correlation Coefficient Acceleration for Modeling and Mapping of Neural Interconnections., , , и . IPDPS Workshops, стр. 223-228. IEEE Computer Society, (2017)A Case Study for an Accelerated DCNN on FPGA-Based Embedded Distributed System., , , , и . IPDPS Workshops, стр. 91-94. IEEE, (2019)Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components., , , , , и . ACM Trans. Reconfigurable Technol. Syst., 14 (3): 15:1-15:33 (2021)On How to Improve FPGA-Based Systems Design Productivity via SDAccel., , , , , и . IPDPS Workshops, стр. 247-252. IEEE Computer Society, (2016)Flex-SFU: Accelerating DNN Activation Functions by Non-Uniform Piecewise Approximation., , и . DAC, стр. 1-6. IEEE, (2023)Mix-GEMM: An efficient HW-SW Architecture for Mixed-Precision Quantized Deep Neural Networks Inference on Edge Devices., , , , , , и . HPCA, стр. 1085-1098. IEEE, (2023)