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A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.

, , , , , , , , , , , , , , , , , , , , , и . ISSCC, стр. 282-283. IEEE, (2008)

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Dong-Shin Shin

Jeonghun Shin

Kirche als Weltforum: zum Dialogverständnis in kirchlichen Dokumenten seit dem Zweiten Vatikanischen Konzil. Uni München, (2009)

Hwa-Ja Shin

Jung-Hyu Shin

Hyeseon Shin

 

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A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme., , , , , и . ESSCIRC, стр. 82-85. IEEE, (2008)A Fast-lock Synchronous Multi-phase Clock Generator based on a Time-to-digital Converter., , , , и . ISCAS, стр. 1-4. IEEE, (2009)A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time., , , , и . CICC, стр. 369-372. IEEE, (2007)2.4 A 7nm High-Performance and Energy-Efficient Mobile Application Processor with Tri-Cluster CPUs and a Sparsity-Aware NPU., , , , , , , , , и 3 other автор(ы). ISSCC, стр. 48-50. IEEE, (2020)Bandwidth-aware DRAM page migration for heterogeneous mobile memory systems., и . ICCE, стр. 1-5. IEEE, (2018)Frequency-independent fast-lock register-controlled DLL with wide-range duty cycle adjuster., , , и . SoCC, стр. 79-82. IEEE, (2010)A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology., , , , , , , , , и 12 other автор(ы). ISSCC, стр. 282-283. IEEE, (2008)A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC., , , , , и . ISSCC, стр. 184-595. IEEE, (2007)A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time., , , и . IEEE Trans. Very Large Scale Integr. Syst., 17 (10): 1461-1469 (2009)High Quality Factor Mode Ordered Dual Foucault Pendulum Gyroscope., , , , , , , , и . IEEE SENSORS, стр. 1-4. IEEE, (2018)