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A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.

W. Yun, H. Lee, D. Shin, S. Kang, J. Yang, H. Lee, D. Lee, S. Sim, Y. Kim, W. Choi, K. Song, S. Shin, H. Choi, H. Moon, S. Kwack, J. Lee, Y. Choi, N. Park, K. Kim, Y. Choi, J. Ahn, and Y. Yang. ISSCC, page 282-283. IEEE, (2008)

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Sopheap Ouk

Ismail Oukid

Khemais Oukhai

Maurice Ochieng Ouko

Xavier Lee Lee

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A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS.H. Lee, W. Yun, Y. Choi, H. Choi, J. Lee, K. Kim, S. Kang, J. Yang, J. Kang, H. Lee and 14 other author(s). ISSCC, page 140-141. IEEE, (2009)A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.W. Yun, H. Lee, D. Shin, S. Kang, J. Yang, H. Lee, D. Lee, S. Sim, Y. Kim, W. Choi and 12 other author(s). ISSCC, page 282-283. IEEE, (2008)

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Disambiguation of "Lee, Hyeng-Ouk"

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A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.

Please choose a person to relate this publication to

Sopheap Ouk

Ismail Oukid

Khemais Oukhai

Maurice Ochieng Ouko

Xavier Lee Lee

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lee, Hyeng-Ouk"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.

Please choose a person to relate this publication to

Sopheap Ouk

Ismail Oukid

Khemais Oukhai

Maurice Ochieng Ouko

Xavier Lee Lee

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.