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Disambiguation of "Shin, Sang-Hoon"

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A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.

, , , , , , , , , , , , , , , , , , , , , and . ISSCC, page 282-283. IEEE, (2008)

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Jong Hoon Shin

Sang-Hoon Song

Sang Hoon Kim

Myoung-Hoon Shin

Sang-Hoon Park

 

Other publications of authors with the same name

Impact of etch angles on cell characteristics in 3D NAND flash memory., , , , , , and . Microelectron. J., (2018)A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS., , , , , , , , , and 14 other author(s). ISSCC, page 140-141. IEEE, (2009)18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution., , , , , , , , , and 11 other author(s). ISSCC, page 316-317. IEEE, (2016)Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM)., , , , , , , , , and 9 other author(s). A-SSCC, page 169-172. IEEE, (2016)A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology., , , , , , , , , and 12 other author(s). ISSCC, page 282-283. IEEE, (2008)A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 52 (1): 250-260 (2017)Integrated modeling of Self-heating of confined geometry (FinFET, NWFET, and NSHFET) transistors and its implications for the reliability of sub-20 nm modern integrated circuits., , , , , and . Microelectron. Reliab., (2018)A partial scan design by unifying structural analysis and testabilities., , and . ISCAS, page 88-91. IEEE, (2000)Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface., , , , , , , , , and 3 other author(s). ISSCC, page 280-281. IEEE, (2008)