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Disambiguation of "Tamura, Hirotaka"

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On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs.

, , , , and . VLSIC, page 1-2. IEEE, (2014)

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Claudia Tamura

Ichiro Tamura

Hitoshi Tamura

Hirotaka Wakatsuki

Hirotaka Yoshida

 

Other publications of authors with the same name

Optimizing effective interconnect capacitance for FPGA power reduction., , and . FPGA, page 11-20. ACM, (2014)Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (5): 1306-1315 (2008)An 8-11 Gb/s Reference-Less Bang-Bang CDR Enabled by "Phase Reset"., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (7): 2129-2138 (2014)A Blind Baud-Rate ADC-Based CDR., , , , and . IEEE J. Solid State Circuits, 48 (12): 3285-3295 (2013)A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS., , , , , and . IEEE J. Solid State Circuits, 45 (6): 1091-1098 (2010)On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs., , , , and . IEEE J. Solid State Circuits, 50 (4): 845-855 (2015)A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 44 (12): 3580-3589 (2009)A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique., , , , , , , , and . IEEE J. Solid State Circuits, 40 (8): 1680-1687 (2005)A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-µm CMOS., , , , , and . IEEE J. Solid State Circuits, 42 (3): 627-636 (2007)Charge recycling for power reduction in FPGA interconnect., , and . FPL, page 1-8. IEEE, (2013)