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Adaptable I/O pad circuit for multiple voltage units bus operation., and . Integr., 36 (1-2): 83-86 (2003)A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells., , and . IEEE Access, (2020)Variability Influence on FinFET-Based On-Chip Memory Data Paths., , , and . J. Low Power Electron., 11 (2): 250-255 (2015)SET and noise fault tolerant circuit design techniques: Application to 7 nm FinFET., , , , and . Microelectron. Reliab., 54 (4): 738-745 (2014)A Circuit-Level SPICE Modeling Strategy for the Simulation of Behavioral Variability in ReRAM., , and . VLSI-SoC, page 1-4. IEEE, (2022)Power supply noise and logic error probability., , , , and . ECCTD, page 152-155. IEEE, (2007)An automotive case study on the limits of approximation for object detection., , , , , , , , , and 2 other author(s). J. Syst. Archit., (2023)Modem Gain-Cell Memories in Advanced Technologies., , and . IOLTS, page 65-68. IEEE, (2018)New reliability mechanisms in memory design for sub-22nm technologies., , , , , , , , , and 7 other author(s). IOLTS, page 111-114. IEEE Computer Society, (2011)Statistical characterization and modeling of random telegraph noise effects in 65nm SRAMs cells., , , , , , , and . SMACD, page 1-4. IEEE, (2017)