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Parallelism exploration for 3D high-efficiency video coding depth modeling mode one.

, , , and . J. Real Time Image Process., 17 (4): 787-797 (2020)

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Monitoring Performance and Power for Application Characterization with the Cache-Aware Roofline Model., , , , , and . PPAM (1), volume 8384 of Lecture Notes in Computer Science, page 747-760. Springer, (2013)MRC-Based RNS Reverse Converters for the Four-Moduli Sets 2n+1, 2n-1, 2n, 22n+1-1 and 2n+1, 2n-1, 22n, 22n+1-1., and . IEEE Trans. Circuits Syst. II Express Briefs, 59-II (4): 244-248 (2012)RNS Reverse Converters for Moduli Sets With Dynamic Ranges up to (8n+1)-bit., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (6): 1487-1500 (2013)Randomised multi-modulo residue number system architecture for double-and-add to prevent power analysis side channel attacks., , , and . IET Circuits Devices Syst., 7 (5): 283-293 (2013)Multicore Parallelism Exploration Targeting 3D-HEVC Intra-Frame Prediction., , , , , and . IEEE Des. Test, 37 (3): 15-21 (2020)A Multifunctional Unit for Designing Efficient RNS-Based Datapaths., , , and . IEEE Access, (2017)GPU-assisted HEVC intra decoder., , , and . J. Real-Time Image Processing, 12 (2): 531-547 (2016)GPU acceleration of the HEVC decoder inter prediction module., , , and . GlobalSIP, page 1245-1249. IEEE, (2015)Multiobjective Frog-Leaping Optimization for the Study of Ancestral Relationships in Protein Data., , and . IEEE Trans. Evol. Comput., 22 (6): 879-893 (2018)Portable LDPC Decoding on Multicores Using OpenCL Applications Corner., , , and . IEEE Signal Process. Mag., 29 (4): 81-109 (2012)