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An Integrated Framework of Design Optimization and Space Minimization for DSP applications., , и . ISCAS (5), стр. 601-604. IEEE, (2003)Performance optimization of multiple memory architectures for DSP., , и . ISCAS (5), стр. 469-472. IEEE, (2002)Partitioning and Retiming of Multi-Dimensional Systems., , и . ISCAS, стр. 227-230. IEEE, (1994)Optimized Address Assignment With Array and Loop Transformations for Minimizing Schedule Length., , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (1): 379-389 (2008)Loop scheduling with timing and switching-activity minimization for VLIW DSP., , , , и . ACM Trans. Design Autom. Electr. Syst., 11 (1): 165-185 (2006)2011 ACM TODAES best paper award., и . ACM Trans. Design Autom. Electr. Syst., 16 (4): 36:1 (2011)Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation., , , , , и . DAC, стр. 350-355. ACM, (2010)General loop fusion technique for nested loops considering timing and code size., , , и . CASES, стр. 190-201. ACM, (2004)Energy-Aware Online Algorithm to Satisfy Sampling Rates with Guaranteed Probability for Sensor Applications., и . HPCC, том 4782 из Lecture Notes in Computer Science, стр. 156-167. Springer, (2007)Loop Distribution and Fusion with Timing and Code Size Optimization for Embedded DSPs., , , , , и . EUC, том 3824 из Lecture Notes in Computer Science, стр. 121-130. Springer, (2005)