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Disambiguation of "Katoh, Kentaroh"

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A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit.

, , and . Asian Test Symposium, page 343-348. IEEE Computer Society, (2010)

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Eishow Katoh

Eishow Katoh

Marcus Katoh

Eishow Katoh

 

Other publications of authors with the same name

A Delay Measurement Technique Using Signature Registers., , , , and . Asian Test Symposium, page 157-162. IEEE Computer Society, (2009)An Analysis of Stochastic Self-Calibration of TDC Using Two Ring Oscillators., , , , , and . Asian Test Symposium, page 140-146. IEEE Computer Society, (2013)Design for Delay Fault Testability of 2-Rail Logic Circuits., , and . IEICE Trans. Inf. Syst., 92-D (2): 336-341 (2009)A Physically Unclonable Function Using Time-to-Digital Converter with Linearity Self-Calibration and its FPGA Implementation., , , , , , , , , and 3 other author(s). ITC-Asia, page 1-6. IEEE, (2023)Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability., , and . DFT, page 31-40. IEEE Computer Society, (2007)Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability., , and . Inf. Media Technol., 3 (4): 704-716 (2008)Innovative Practices Track: Innovative Analog Circuit Testing Technologies., , , , , , , , , and 8 other author(s). VTS, page 1. IEEE, (2022)Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift., , and . IOLTS, page 203-204. IEEE Computer Society, (2005)Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices., and . ETS, page 69-74. IEEE Computer Society, (2006)A low area calibration technique of TDC using variable clock generator for accurate on-line delay measurement., and . ISQED, page 430-434. IEEE, (2015)