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Другие публикации лиц с тем же именем

Fault Tolerant Design Using Error Correcting Code for Multilayer Neural Networks., и . DFT, стр. 177-184. IEEE Computer Society, (1994)A Checkpointing Method with Small Checkpoint Latency., , и . IEICE Trans. Inf. Syst., 91-D (3): 857-861 (2008)Design for Delay Fault Testability of 2-Rail Logic Circuits., , и . IEICE Trans. Inf. Syst., 92-D (2): 336-341 (2009)Scan FF Reordering for Test Volume Reduction in Chiba-scan Architecture., , и . IPSJ Trans. Syst. LSI Des. Methodol., (2011)Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding., , и . J. Electron. Test., 25 (1): 97-105 (2009)Concurrent Core Test for Test Cost Reduction Using Merged Test Set and Scan Tree., и . ICCD, стр. 143-146. IEEE Computer Society, (2005)A Delay Measurement Technique Using Signature Registers., , , , и . Asian Test Symposium, стр. 157-162. IEEE Computer Society, (2009)Path Delay Fault Test Set for Two-Rail Logic Circuits., и . PRDC, стр. 347-348. IEEE Computer Society, (2008)Fault-Tolerant Properties of Generalized Hierarchical Completely-Connected Networks., , и . PRDC, стр. 137-144. IEEE Computer Society, (2002)Efficient Test Data Decompression for System-on-a-Chip Using an Embedded FPGA Core., и . DFT, стр. 503-510. IEEE Computer Society, (2003)