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10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS.

A. Elkholy, M. Talegaonkar, T. Anand, and P. Hanumolu. ISSCC, page 1-3. IEEE, (2015)

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Davinder Kumar Anand

Amar Frank Anand

Madhankumar Anandhakrishnan

Anand Raghavachar

Anand Roy

Other publications of authors with the same name

A 3.5-mV Input Single-Inductor Self-Starting Boost Converter With Loss-Aware MPPT for Efficient Autonomous Body-Heat Energy Harvesting.S. Bose, T. Anand, and M. Johnston. IEEE J. Solid State Circuits, 56 (6): 1837-1848 (2021)A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter.M. Talegaonkar, T. Anand, A. Elkholy, A. Elshazly, R. Nandwana, S. Saxena, B. Young, W. Choi, and P. Hanumolu. VLSIC, page 1-2. IEEE, (2014)A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement.R. Nandwana, T. Anand, S. Saxena, S. Kim, M. Talegaonkar, A. Elkholy, W. Choi, A. Elshazly, and P. Hanumolu. VLSIC, page 1-2. IEEE, (2014)3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS.T. Anand, M. Talegaonkar, A. Elkholy, S. Saxena, A. Elshazly, and P. Hanumolu. ISSCC, page 1-3. IEEE, (2015)A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz In-band noise using time amplifier based TDC.A. Elkholy, T. Anand, W. Choi, A. Elshazly, and P. Hanumolu. VLSIC, page 1-2. IEEE, (2014)Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers.A. Elkholy, M. Talegaonkar, T. Anand, and P. Hanumolu. IEEE J. Solid State Circuits, 50 (12): 3160-3174 (2015)A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links.W. Choi, T. Anand, G. Shu, A. Elshazly, and P. Hanumolu. IEEE J. Solid State Circuits, 50 (3): 737-748 (2015)A Fully Decoupled LC Tank VCO Topology for Amplitude Boosted Low Phase Noise Operation.B. Sadhu, T. Anand, and S. Reynolds. IEEE J. Solid State Circuits, 53 (9): 2488-2499 (2018)A 10-Gb/s/ch, 0.6-pJ/bit/mm Power Scalable Rapid-ON/OFF Transceiver for On-Chip Energy Proportional Interconnects.D. Wei, T. Anand, G. Shu, J. Schutt-Ainé, and P. Hanumolu. IEEE J. Solid State Circuits, 53 (3): 873-883 (2018)8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS.G. Shu, W. Choi, S. Saxena, T. Anand, A. Elshazly, and P. Hanumolu. ISSCC, page 150-151. IEEE, (2014)

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Disambiguation of "Anand, Tejasvi"