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Disambiguation of "Pamula, Venkata Rajesh"

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A 172 µW Compressively Sampled Photoplethysmographic (PPG) Readout ASIC With Heart Rate Estimation Directly From Compressively Sampled Data.

, , , , , , , and . IEEE Trans. Biomed. Circuits Syst., 11 (3): 487-496 (2017)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Danuta Pamula

Rajesh Saiju

Hybrid Power System Modelling - Simulation and Energy Management Unit Development. Uni Kassel, (2008)

Rajesh Chitta

Rajesh Saiju

Rajesh Narasimha

 

Other publications of authors with the same name

A 680 nA ECG Acquisition IC for Leadless Pacemaker Applications., , , , , , , and . IEEE Trans. Biomed. Circuits Syst., 8 (6): 779-786 (2014)A 172 µW Compressively Sampled Photoplethysmographic (PPG) Readout ASIC With Heart Rate Estimation Directly From Compressively Sampled Data., , , , , , , and . IEEE Trans. Biomed. Circuits Syst., 11 (3): 487-496 (2017)A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS., , , , and . ISSCC, page 230-232. IEEE, (2019)A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS., , , , , , and . IEEE J. Solid State Circuits, 55 (7): 1749-1761 (2020)Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control., , , , , , and . IEEE J. Solid State Circuits, 57 (1): 90-102 (2022)22.4 A 172µW compressive sampling photoplethysmographic readout with embedded direct heart-rate and variability extraction from compressively sampled data., , , , , , , and . ISSCC, page 386-387. IEEE, (2016)A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor., , , , , , and . ISSCC, page 302-304. IEEE, (2018)A Bidirectional Brain Computer Interface with 64-Channel Recording, Resonant Stimulation and Artifact Suppression in Standard 65nm CMOS., , , , , and . ESSCIRC, page 77-80. IEEE, (2019)A 0.0023 mm2/ch. Delta-Encoded, Time-Division Multiplexed Mixed-Signal ECoG Recording Architecture With Stimulus Artifact Suppression., , , , , and . IEEE Trans. Biomed. Circuits Syst., 14 (2): 319-331 (2020)An All-Digital Fused PLL-Buck Architecture for 82% Average Vdd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor., , , , , , and . IEEE J. Solid State Circuits, 54 (11): 3215-3225 (2019)