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Disambiguation of "da Luz Reis, Ricardo Augusto"

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Fast and Scalable I/O Pin Assignment with Divide-and-Conquer and Hungarian Matching.

, , , , , and . NEWCAS, page 74-77. IEEE, (2020)

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Andre Wiesmann da Silva Reis

Augusto Mangini

Augusto Lautz

Augusto Araújo

Augusto Minatta

 

Other publications of authors with the same name

Drive Strength Aware Cell Movement Techniques for Timing Driven Placement., , , , and . ISPD, page 73-80. ACM, (2016)Analyzing the electromigration effects on different metal layers and different wire lengths., , , and . ICECS, page 682-685. IEEE, (2014)Impact of different transistor arrangements on gate variability., , , , , and . Microelectron. Reliab., (2018)Evaluation of heavy-ion impact in bulk and FDSOI devices under ZTC condition., , , , and . Microelectron. Reliab., (2017)Power and Timing Driven Physical Design Automation.. PATMOS, volume 2799 of Lecture Notes in Computer Science, page 348-357. Springer, (2003)Lookup-based Remote Laboratory for FPGA Digital Design Prototyping., , and . VIRTUAL-LAB, page 3-11. INSTICC Press, (2004)Multi-Level Design Influences on Robustness Evaluation of 7nm FinFET Technology., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 67-I (2): 553-564 (2020)Improving Critical Path Identification in Functional Timing Analysis., , , and . SBCCI, page 297-302. IEEE Computer Society, (2003)Fast and Scalable I/O Pin Assignment with Divide-and-Conquer and Hungarian Matching., , , , , and . NEWCAS, page 74-77. IEEE, (2020)Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs., , , , , and . VLSI-SoC, volume 240 of IFIP, page 179-194. Springer, (2005)