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Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network.

Y. Xie, S. Eachempati, A. Yanamandra, V. Narayanan, and M. Irwin. NANOARCH, page 51-56. IEEE Computer Society, (2009)

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Aditya Aryasomayajula

Aditya Devarakonda

Aditya Malik

Aditya Kumar

Aditya Kalyanpur

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Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network.Y. Xie, S. Eachempati, A. Yanamandra, V. Narayanan, and M. Irwin. NANOARCH, page 51-56. IEEE Computer Society, (2009)Optimizing power and performance for reliable on-chip networks.A. Yanamandra, S. Eachempati, N. Soundararajan, V. Narayanan, M. Irwin, and R. Krishnan. ASP-DAC, page 431-436. IEEE, (2010)RAFT: A router architecture with frequency tuning for on-chip networks.A. Mishra, A. Yanamandra, R. Das, S. Eachempati, R. Iyer, N. Vijaykrishnan, and C. Das. J. Parallel Distributed Comput., 71 (5): 625-640 (2011)Evaluating the role of scratchpad memories in chip multiprocessors for sparse matrix computations.A. Yanamandra, B. Cover, P. Raghavan, M. Irwin, and M. Kandemir. IPDPS, page 1-10. IEEE, (2008)On the Effects of Process Variation in Network-on-Chip Architectures.C. Nicopoulos, S. Srinivasan, A. Yanamandra, D. Park, V. Narayanan, C. Das, and M. Irwin. IEEE Trans. Dependable Secur. Comput., 7 (3): 240-254 (2010)A low-power phase change memory based hybrid cache architecture.P. Mangalagiri, K. Sarpatwari, A. Yanamandra, V. Narayanan, Y. Xie, M. Irwin, and O. Karim. ACM Great Lakes Symposium on VLSI, page 395-398. ACM, (2008)In-Network Caching for Chip Multiprocessors.A. Yanamandra, M. Irwin, V. Narayanan, M. Kandemir, and S. Narayanan. HiPEAC, volume 5409 of Lecture Notes in Computer Science, page 373-388. Springer, (2009)Analysis and solutions to issue queue process variation.N. Soundararajan, A. Yanamandra, C. Nicopoulos, N. Vijaykrishnan, A. Sivasubramaniam, and M. Irwin. DSN, page 11-21. IEEE Computer Society, (2008)

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Disambiguation of "Yanamandra, Aditya"

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Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network.

Please choose a person to relate this publication to

Aditya Aryasomayajula

Aditya Devarakonda

Aditya Malik

Aditya Kumar

Aditya Kalyanpur

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Yanamandra, Aditya"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network.

Please choose a person to relate this publication to

Aditya Aryasomayajula

Aditya Devarakonda

Aditya Malik

Aditya Kumar

Aditya Kalyanpur

Other publications of authors with the same name

Disambiguation

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URL
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Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network.