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An innovative die to wafer 3D integration scheme: Die to wafer oxide or copper direct bonding with planarised oxide inter-die filling., , , , , , , , , and 5 other author(s). 3DIC, page 1-4. IEEE, (2009)Modelling of Through Silicon Via RF performance and impact on signal transmission in 3D integrated circuits., , , , , , , , , and 3 other author(s). 3DIC, page 1-7. IEEE, (2009)POPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems., , , , , , , , , and 5 other author(s). DATE, page 1456-1461. IEEE, (2020)First integration of Cu TSV using die-to-wafer direct bonding and planarization., , , , , , , , , and 3 other author(s). 3DIC, page 1-5. IEEE, (2009)Development of a permittivity extraction method for ultra low k dielectrics integrated in advanced interconnects., , , , , , and . Microelectron. Reliab., 47 (4-5): 769-772 (2007)A successful implementation of dual damascene architecture to copper TSV for 3D high density applications., , , , , , and . 3DIC, page 1-4. IEEE, (2010)Specificities of linear Si QD arrays integration and characterization., , , , , , , , , and 11 other author(s). VLSI Technology and Circuits, page 415-416. IEEE, (2022)