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Design for Test With Unreliable Memories by Restoring the Beauty of Randomness.

, , and . IEEE Des. Test, 39 (2): 112-120 (2022)

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Hardware-efficient random sampling of fourier-sparse signals., , , and . ISCAS, page 269-272. IEEE, (2012)Feedback-Aware Precoding for Millimeter Wave Massive MIMO Systems., , , and . CoRR, (2018)A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (2): 329-340 (2018)Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (6): 806-817 (2016)Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space., , , , , and . IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 67-I (4): 1207-1217 (2020)Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs, , , , , , , , , and . ACM Trans. Embedded Comput. Syst., 14 (2): 33:1--33:23 (2015)Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platforms., , , , , and . DATE, page 396-399. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Lora Digital Receiver Analysis and Implementation., , , and . ICASSP, page 1498-1502. IEEE, (2019)Sliding Window Spectrum Sensing for Full-Duplex Cognitive Radios with Low Access-Latency., , , and . VTC Spring, page 1-5. IEEE, (2016)Digital predistortion of hardware impairments for full-duplex transceivers., , and . GlobalSIP, page 878-882. IEEE, (2017)