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Analyzing the behavior of FinFET SRAMs with resistive defects., , , and . VLSI-SoC, page 1-6. IEEE, (2017)A DfT Strategy for Detecting Emerging Faults in RRAMs., , and . VLSI-SoC (Selected Papers), volume 661 of IFIP Advances in Information and Communication Technology, page 93-111. Springer, (2021)Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG., , , , , , , , , and 1 other author(s). LATS, page 1-6. IEEE Computer Society, (2015)Evaluating a New RRAM Manufacturing Test Strategy., , , and . LATS, page 1-6. IEEE, (2023)Evaluating the Impact of Process Variation on RRAMs., , , , , , and . LATS, page 1-6. IEEE, (2021)A Comparative Study Between FinFET and CMOS-Based SRAMs under Resistive Defects., , , , and . LATS, page 1-6. IEEE, (2019)Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits., , , , , , , , , and 2 other author(s). J. Electron. Test., 32 (3): 273-289 (2016)Improving the Detection of Undefined State Faults in FinFET SRAMs., , , , , , and . DTIS, page 1-6. IEEE, (2021)Validating a DFT Strategy's Detection Capability regarding Emerging Faults in RRAMs., , and . VLSI-SoC, page 1-6. IEEE, (2021)Evaluating the Impact of Resistive Defects on FinFET-Based SRAMs., , , and . VLSI-SoC (Selected Papers), volume 500 of IFIP Advances in Information and Communication Technology, page 22-45. Springer, (2017)