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A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS., , , , , , and . VLSIC, page 346-. IEEE, (2015)A 3-D-Integrated Silicon Photonic Microring-Based 112-Gb/s PAM-4 Transmitter With Nonlinear Equalization and Thermal Control., , , , , , , and . IEEE J. Solid State Circuits, 56 (1): 19-29 (2021)8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew., , , , , , , and . IEEE J. Solid State Circuits, 40 (1): 80-88 (2005)A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file., , , , , and . IEEE J. Solid State Circuits, 37 (5): 624-632 (2002)A 3D-integrated 8λ × 32 Gbps λ Silicon Photonic Microring-based DWDM Transmitter., , , , , , , , , and 4 other author(s). CICC, page 1-2. IEEE, (2023)Energy-efficient dynamic circuit design in the presence of crosstalk noise., and . ISLPED, page 24-29. ACM, (1999)Strong Injection Locking in Low- Q LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver., , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (8): 1818-1829 (2009)Silicon Photonic Microring-Based 4 × 112 Gb/s WDM Transmitter With Photocurrent-Based Thermal Control in 28-nm CMOS., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 57 (4): 1187-1198 (2022)11.6 A 100Gb/s-8.3dBm-Sensitivity PAM-4 Optical Receiver with Integrated TIA, FFE and Direct-Feedback DFE in 28nm CMOS., , , , and . ISSCC, page 190-192. IEEE, (2021)A 112 Gb/s PAM4 Transmitter with Silicon Photonics Microring Modulator and CMOS Driver., , , , , , , , , and . OFC, page 1-3. IEEE, (2019)