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Enhanced bus invert encodings for low-power.

, , и . ISCAS (5), стр. 25-28. IEEE, (2002)

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Terakel Eroman Unni

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

 

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Domino logic synthesis minimizing crosstalk., , и . DAC, стр. 280-285. ACM, (2000)Noise-aware power optimization for on-chip interconnect., , , , и . ISLPED, стр. 108-113. ACM, (2000)Algorithmic Techniques for Logic Synthesis of Low Power VLSI Circuits. University of Illinois Urbana-Champaign, USA, (1998)Low power logic synthesis for XOR based circuits., и . ICCAD, стр. 570-574. IEEE Computer Society / ACM, (1997)Noise-aware interconnect power optimization in domino logic synthesis., , , , и . IEEE Trans. Very Large Scale Integr. Syst., 11 (1): 79-89 (2003)Low power logic synthesis under a general delay model., , и . ISLPED, стр. 209-214. ACM, (1998)Decomposition of Bus-Invert Coding for Low-Power I/O., , , и . Journal of Circuits, Systems, and Computers, 10 (1-2): 101-112 (2000)Enhanced bus invert encodings for low-power., , и . ISCAS (5), стр. 25-28. IEEE, (2002)Characterizing Individual Gate Power Sensitivity in Low Power Design., , и . VLSI Design, стр. 625-. IEEE Computer Society, (1999)Automated Phase Assignment for the Synthesis of Low Power Domino Circuits., и . DAC, стр. 379-384. ACM Press, (1999)