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Disambiguation of "Nomura, Masahiro"

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Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits.

, , , and . IEEE J. Solid State Circuits, 49 (2): 536-544 (2014)

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Toru Nomura

Masahiro Noguchi

Masahiro Ogawa

Yutaka Nomura

Masahiro Yoshida

 

Other publications of authors with the same name

Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs., , , , , , , , , and . IEEE J. Solid State Circuits, 46 (4): 806-814 (2011)Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits., , , , , and . CICC, page 1-4. IEEE, (2012)An Automatic Bi-Directional Bus Repeater Control Scheme Using Dynamic Collaborative Driving Techniques., , , , , , and . IEICE Trans. Electron., 89-C (3): 334-341 (2006)A Simple Heuristic for Bayesian Optimization with A Low Budget., and . CoRR, (2019)A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates., , , , , , and . DAC, page 984-989. ACM, (2011)Optimal Fixed-Budget Best Arm Identification using the Augmented Inverse Probability Weighting Estimator in Two-Armed Gaussian Bandits with Unknown Variances., , , , , and . CoRR, (2022)Efficient Hyperparameter Optimization under Multi-Source Covariate Shift., and . CIKM, page 1376-1385. ACM, (2021)Warm Starting CMA-ES for Hyperparameter Optimization., , , , and . AAAI, page 9188-9196. AAAI Press, (2021)Natural Evolution Strategy for Unconstrained and Implicitly Constrained Problems with Ridge Structure., and . SSCI, page 1-7. IEEE, (2021)13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO., , , , , , , and . ISSCC, page 486-488. IEEE, (2012)