Author of the publication

FastYield: variation-aware, layout-driven simultaneous binding and module selection for performance yield optimization.

, , and . ASP-DAC, page 61-66. IEEE, (2009)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

AutoScaleDSE: A Scalable Design Space Exploration Engine for High-Level Synthesis., , , and . ACM Trans. Reconfigurable Technol. Syst., 16 (3): 46:1-46:30 (September 2023)Algorithm/Accelerator Co-Design and Co-Search for Edge AI., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (7): 3064-3070 (2022)An Efficient Compiler Framework for Cache Bypassing on GPUs., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (10): 1677-1690 (2015)Exploring HW/SW Co-Design for Video Analysis on CPU-FPGA Heterogeneous Systems., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (6): 1606-1619 (2022)VecQ: Minimal Loss DNN Model Compression With Vectorized Weight Quantization., , , , , and . IEEE Trans. Computers, 70 (5): 696-710 (2021)ASAP: Accelerated Short-Read Alignment on Programmable Hardware., , , , , , and . IEEE Trans. Computers, 68 (3): 331-346 (2019)A Routing Approach to Reduce Glitches in Low Power FPGAs., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (2): 235-240 (2010)ASAP: Accelerated Short-Read Alignment on Programmable Hardware., , , , , , and . CoRR, (2018)A Hardware-Efficient Block Matching Algorithm and Its Hardware Design for Variable Block Size Motion Estimation in Ultra-High-Definition Video Encoding., , , , and . ACM Trans. Design Autom. Electr. Syst., 24 (2): 15:1-15:21 (2019)ScaleHLS: Scalable High-Level Synthesis through MLIR., , , , , , and . CoRR, (2021)