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Bridging the domains of high-level and logic synthesis.. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (5): 582-596 (2002)ESWEEK 2009 special issue introduction.. Des. Autom. Embed. Syst., 14 (3): 161 (2010)Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems., , , , , , and . Des. Autom. Embed. Syst., 10 (2-3): 105-125 (2005)Introductions to special issue on ESWEEK 2011., , , , , , and . Des. Autom. Embed. Syst., 17 (2): 215-219 (2013)Embedded Java: techniques and applications (tutorial abstract)., , and . ICCAD, page 613. IEEE Computer Society, (1999)High-Level State Machine Specification and Synthesis., and . ICCD, page 536-539. IEEE Computer Society, (1992)Timing analysis in high-level synthesis., and . ICCAD, page 349-354. IEEE Computer Society / ACM, (1992)State-based power analysis for systems-on-chip., and . DAC, page 638-641. ACM, (2003)High-level synthesis in an industrial environment., , , , , , and . IBM J. Res. Dev., 39 (1-2): 131-148 (1995)Observable Time Windows: Verifying High-Level Synthesis Results., and . IEEE Des. Test Comput., 14 (2): 40-50 (1997)