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Evaluating programmable architectures for imaging and vision applications.

, , , , , and . MICRO, page 52:1-52:13. IEEE Computer Society, (2016)

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Transforming a linear algebra core to an FFT accelerator., , and . ASAP, page 175-184. IEEE Computer Society, (2013)EIE: Efficient Inference Engine on Compressed Deep Neural Network., , , , , , and . ISCA, page 243-254. IEEE Computer Society, (2016)On the Efficiency of Register File versus Broadcast Interconnect for Collective Communications in Data-Parallel Hardware Accelerators., , and . SBAC-PAD, page 19-26. IEEE Computer Society, (2012)Improving energy efficiency of DRAM by exploiting half page row access., , , , and . MICRO, page 27:1-27:12. IEEE Computer Society, (2016)Rethinking Floating Point Overheads for Mixed Precision DNN Accelerators., , , , and . MLSys, mlsys.org, (2021)Retrospective: EIE: Efficient Inference Engine on Sparse and Compressed Neural Network., , , , , , and . CoRR, (2023)A Highly Efficient Multicore Floating-Point FFT Architecture Based on Hybrid Linear Algebra/FFT Cores., , and . J. Signal Process. Syst., 77 (1-2): 169-190 (2014)Plasticine: A Reconfigurable Architecture For Parallel Paterns., , , , , , , , and . ISCA, page 389-402. ACM, (2017)A Linear Algebra Core Design for Efficient Level-3 BLAS., , , , , and . ASAP, page 149-152. IEEE Computer Society, (2012)A high-performance, low-power linear algebra core., , and . ASAP, page 35-42. IEEE Computer Society, (2011)