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A power-efficient 3-D on-chip interconnect for multi-core accelerators with stacked L2 cache.

, , , , and . DATE, page 1465-1468. IEEE, (2016)

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PLEASURE: a computer program for simple/multiple constrained/unconstrained folding of Programmable Logic Arrays., and . DAC, page 530-537. ACM/IEEE, (1983)3.5-D integration: A case study., , , , and . ISCAS, page 2087-2090. IEEE, (2013)Hardware/Software Co-Design, and . Proceedings of the IEEE, (1997)Temperature-aware runtime power management for chip-multiprocessors with 3-D stacked cache., , , and . ISQED, page 163-170. IEEE, (2014)Memristor-based devices for sensing., , , , and . ISCAS, page 2257-2260. IEEE, (2014)Characterization of memristive Poly-Si Nanowires via empirical physical modelling., , , , and . ISCAS, page 1675-1678. IEEE, (2010)Design aspects of carry lookahead adders with vertically-stacked nanowire transistors., , , and . ISCAS, page 1715-1718. IEEE, (2010)A Sound and Complete Axiomatization of Majority-n Logic., , , and . IEEE Trans. Computers, 65 (9): 2889-2895 (2016)Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms., , , , and . DAC, page 247-252. ACM Press, (1999)An integrated platform for differential electrochemical and ISFET sensing., , , and . ISCAS, page 2875-2878. IEEE, (2016)