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Using a Hardware Simulation Engine for Custom MOS Structured Designs., , , and . IBM J. Res. Dev., 28 (5): 564-571 (1984)The EVE companion simulator., , , and . EURO-DAC, page 290-295. IEEE Computer Society, (1990)A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 32 (11): 1676-1682 (1997)Formal verification - prove it or pitch it., , , , , , , , and . DAC, page 710-711. ACM, (2003)SLS-a fast switch-level simulator for MOS., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 7 (8): 838-849 (1988)Blue Gene: A vision for protein science using a petaflop supercomputer., , , , , , , , , and 42 other author(s). IBM Syst. J., 40 (2): 310-327 (2001)Transistor sizing of custom high-performance digital circuits with parametric yield considerations., , , , and . DAC, page 781-786. ACM, (2010)The IBM Engineering Verification Engine., , , and . DAC, page 218-224. ACM, (1988)First-Order Incremental Block-Based Statistical Timing Analysis., , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (10): 2170-2180 (2006)SLS - a fast switch level simulator for verification and fault coverage analysis., , , , and . DAC, page 164-170. IEEE Computer Society Press, (1986)