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Disambiguation of "Krishnamurthy, Ram"

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A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition.

, , , , , , , , , , , and . VLSI Circuits, page 234-. IEEE, (2019)

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Mahalakshmi Krishnamurthy

Adarsh Krishnamurthy

Arvind Krishnamurthy

Ram Gopal

Johann Ram

 

Other publications of authors with the same name

ECMDB: The E. coli Metabolome Database., , , , , , , , , and . Nucleic Acids Res., 41 (Database-Issue): 625-630 (2013)A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (6): 646-649 (2006)A robust alternate repeater technique for high performance busses in the multi-core era., , , , and . ISCAS, page 372-375. IEEE, (2008)Dynamic addressing memory arrays with physical locality., , , , and . MICRO, page 161-170. ACM/IEEE Computer Society, (2002)Near Threshold Voltage (NTV) Computing: Computing in the Dark Silicon Era., , and . IEEE Des. Test, 34 (2): 24-30 (2017)Optimized Fused Floating-Point Many-Term Dot-Product Hardware for Machine Learning Accelerators., , , , and . ARITH, page 84-87. IEEE, (2019)Tutorial: Design of Power Efficient VLSI Arithmetic: Speed and Power Trade-Offs., and . IEEE Symposium on Computer Arithmetic, page 280. IEEE Computer Society, (2003)A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS., , , and . VLSI Design, page 301-306. IEEE Computer Society, (2009)Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations., , , , , , and . BioCAS, page 1-5. IEEE, (2017)Ultra-low energy circuit building blocks for security technologies., , , and . DATE, page 391-394. IEEE, (2018)