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Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video.

K. Mizuno, H. Noguchi, G. He, Y. Terachi, T. Kamino, H. Kawaguchi, и M. Yoshimoto. FPL, стр. 608-611. IEEE Computer Society, (2010)

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Hiroki Takahashi

Masahiro Noguchi

Hiroki Kawamura

Yoshiko Noguchi

Shozo Noguchi

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Data-Intensive Sound Acquisition System with Large-scale Microphone Array.H. Noguchi, T. Takagi, K. Kugata, S. Izumi, M. Yoshimoto, и H. Kawaguchi. J. Inf. Process., (2011)A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition.K. Mizuno, H. Noguchi, G. He, Y. Terachi, T. Kamino, T. Fujinaga, S. Izumi, Y. Ariki, H. Kawaguchi, и M. Yoshimoto. IEICE Trans. Electron., 94-C (4): 448-457 (2011)Live demonstration: Intelligent ubiquitous sensor network for sound acquisition.K. Kugata, T. Takagi, H. Noguchi, M. Yoshimoto, и H. Kawaguchi. ISCAS, стр. 1413. IEEE, (2010)A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing.H. Noguchi, Y. Iguchi, H. Fujiwara, Y. Morita, K. Nii, H. Kawaguchi, и M. Yoshimoto. ISVLSI, стр. 107-112. IEEE Computer Society, (2007)Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video.K. Mizuno, H. Noguchi, G. He, Y. Terachi, T. Kamino, H. Kawaguchi, и M. Yoshimoto. FPL, стр. 608-611. IEEE Computer Society, (2010)Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures.S. Fujita, H. Noguchi, K. Ikegami, S. Takeda, K. Nomura, и K. Abe. ISIC, стр. 316-319. IEEE, (2014)Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential.H. Noguchi, Y. Iguchi, H. Fujiwara, S. Okumura, K. Nii, H. Kawaguchi, и M. Yoshimoto. IPSJ Trans. Syst. LSI Des. Methodol., (2011)Network theory-based accident scenario analysis for hazardous material transport: A case study of liquefied petroleum gas transport in japan.H. Noguchi, S. Hienuki, и M. Fuse. Reliab. Eng. Syst. Saf., (2020)A Dependable SRAM with 7T/14T Memory Cells.H. Fujiwara, S. Okumura, Y. Iguchi, H. Noguchi, H. Kawaguchi, и M. Yoshimoto. IEICE Trans. Electron., 92-C (4): 423-432 (2009)VLSI Architecture of GMM Processing and Viterbi Decoder for 60, 000-Word Real-Time Continuous Speech Recognition.H. Noguchi, K. Miura, T. Fujinaga, T. Sugahara, H. Kawaguchi, и M. Yoshimoto. IEICE Trans. Electron., 94-C (4): 458-467 (2011)

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