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Disambiguation of "Hlawiczka, Andrzej"

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How to reduce size of a signature-based diagnostic dictionary used for testing of connections.

, , and . DDECS, page 201-204. IEEE Computer Society, (2010)

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Helmut Hlawiczka

Andrzej Piotrowski

Andrzej Tomczyk

Andrzej Szczerbakow

Andrzej Lingas

 

Other publications of authors with the same name

Optimized Synthesis of Self-Testable Finite State Machines (FSM) Using BIST-PST Structures in Altera Structures., and . FPL, volume 849 of Lecture Notes in Computer Science, page 120-122. Springer, (1994)Test-per-Clock Detection, Localization and Identification of Interconnect Faults., , , and . ETS, page 233-238. IEEE Computer Society, (2006)Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor., , , , , and . J. Electron. Test., 20 (1): 109-122 (2004)Efficient test pattern generators based on specific cellular automata structures., and . Microelectron. Reliab., 42 (6): 975-983 (2002)Parallel Signature Analyzers Using Hybrid Design of Their Linear Feedbacks.. IEEE Trans. Computers, 41 (12): 1562-1571 (1992)Fast and low-area TPGs based on T-type flip-flops can be easily integrated to the scan path., , and . ETW, page 161-166. IEEE Computer Society, (2000)Compression of multiple-valued data serial streams by means of parallel LFSR signature analyzer.. Fehlertolerierende Rechensysteme, volume 84 of Informatik-Fachberichte, page 404-416. Springer, (1984)Low Cost Bist for Edac Circuits., and . Asian Test Symposium, page 410-415. IEEE Computer Society, (1997)Interconnect Faults Identification and Localization Using Modified Ring LFSRs., , , and . DDECS, page 247-250. IEEE Computer Society, (2008)A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits., and . EDCC, volume 1667 of Lecture Notes in Computer Science, page 321-338. Springer, (1999)