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A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI.

B. Zimmer, Y. Lee, A. Puggelli, J. Kwak, R. Jevtic, B. Keller, S. Bailey, M. Blagojevic, P. Chiu, H. Le, P. Chen, N. Sutardja, R. Avizienis, A. Waterman, B. Richards, P. Flatresse, E. Alon, K. Asanovic, and B. Nikolic. VLSIC, page 316-. IEEE, (2015)

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Rolf-Walter Briant

Benoît Briand

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Annette Brians

Brian Alexander

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Reprogrammable Redundancy for SRAM-Based Cache Vmin Reduction in a 28-nm RISC-V Processor.B. Zimmer, P. Chiu, B. Nikolic, and K. Asanovic. IEEE J. Solid State Circuits, 52 (10): 2589-2600 (2017)Joint impact of random variations and RTN on dynamic writeability in 28nm bulk and FDSOI SRAM.B. Zimmer, O. Thomas, S. Toh, T. Vincent, K. Asanovic, and B. Nikolic. ESSDERC, page 98-101. IEEE, (2014)Simba: scaling deep-learning inference with chiplet-based architecture.Y. Shao, J. Clemons, R. Venkatesan, B. Zimmer, M. Fojtik, N. Jiang, B. Keller, A. Klinefelter, N. Pinckney, P. Raina and 7 other author(s). Commun. ACM, 64 (6): 107-116 (2021)Resilient Design Techniques for Improving Cache Energy Efficiency.B. Zimmer. University of California, Berkeley, USA, (2015)Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture.Y. Shao, J. Clemons, R. Venkatesan, B. Zimmer, M. Fojtik, N. Jiang, B. Keller, A. Klinefelter, N. Pinckney, P. Raina and 7 other author(s). MICRO, page 14-27. ACM, (2019)A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator.J. Poulton, J. Wilson, W. Turner, B. Zimmer, X. Chen, S. Kudva, S. Song, S. Tell, N. Nedovic, W. Zhao and 3 other author(s). IEEE J. Solid State Circuits, 54 (1): 43-54 (2019)A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm.B. Keller, R. Venkatesan, S. Dai, S. Tell, B. Zimmer, C. Sakr, W. Dally, C. Gray, and B. Khailany. IEEE J. Solid State Circuits, 58 (4): 1129-1141 (2023)AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies.H. Chen, W. Turner, S. Song, K. Zhu, G. Kokai, B. Zimmer, C. Gray, B. Khailany, D. Pan, and H. Ren. ISPD, page 175-183. ACM, (2022)On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC.M. Cochet, A. Puggelli, B. Keller, B. Zimmer, M. Blagojevic, S. Clerc, P. Roche, J. Autran, and B. Nikolic. A-SSCC, page 125-128. IEEE, (2016)A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET.M. Fojtik, B. Keller, A. Klinefelter, N. Pinckney, S. Tell, B. Zimmer, T. Raja, K. Zhou, W. Dally, and B. Khailany. ASYNC, page 27-35. IEEE, (2019)

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Disambiguation of "Zimmer, Brian"

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A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI.

Please choose a person to relate this publication to

Rolf-Walter Briant

Benoît Briand

Ursula Brian

Annette Brians

Brian Alexander

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Zimmer, Brian"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI.

Please choose a person to relate this publication to

Rolf-Walter Briant

Benoît Briand

Ursula Brian

Annette Brians

Brian Alexander

Other publications of authors with the same name

Disambiguation

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URL
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A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI.