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A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI.

B. Zimmer, Y. Lee, A. Puggelli, J. Kwak, R. Jevtic, B. Keller, S. Bailey, M. Blagojevic, P. Chiu, H. Le, P. Chen, N. Sutardja, R. Avizienis, A. Waterman, B. Richards, P. Flatresse, E. Alon, K. Asanovic, and B. Nikolic. VLSIC, page 316-. IEEE, (2015)

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Ben Koch

Ben Elsner

Ben Abendroth

Ben Weise

Ben Schweizer

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Reply to discussion by B. Keller and R. Nance.B. Keller, and R. Nance. Journal of Software Maintenance, 7 (5): 379-380 (1995)A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI.M. Blagojevic, M. Cochet, B. Keller, P. Flatresse, A. Vladimirescu, and B. Nikolic. VLSI Circuits, page 1-2. IEEE, (2016)A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI.B. Keller, M. Cochet, B. Zimmer, J. Kwak, A. Puggelli, Y. Lee, M. Blagojevic, S. Bailey, P. Chiu, D. Dabbelt and 4 other author(s). IEEE J. Solid State Circuits, 52 (7): 1863-1875 (2017)Verifying High-Level Latency-Insensitive Designs with Formal Model Checking.S. Dai, A. Klinefelter, H. Ren, R. Venkatesan, B. Keller, N. Pinckney, and B. Khailany. CoRR, (2021)MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification.V. Chhabria, Y. Zhang, H. Ren, B. Keller, B. Khailany, and S. Sapatnekar. DATE, page 1825-1828. IEEE, (2021)HEAT: Hardware-Efficient Automatic Tensor Decomposition for Transformer Compression.J. Gu, B. Keller, J. Kossaifi, A. Anandkumar, B. Khailany, and D. Pan. CoRR, (2022)Problem C: GPU Accelerated Logic Re-simulation : (Invited Talk).Y. Zhang, H. Ren, B. Keller, and B. Khailany. ICCAD, page 70:1-70:4. IEEE, (2020)On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC.M. Cochet, A. Puggelli, B. Keller, B. Zimmer, M. Blagojevic, S. Clerc, P. Roche, J. Autran, and B. Nikolic. A-SSCC, page 125-128. IEEE, (2016)A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET.M. Fojtik, B. Keller, A. Klinefelter, N. Pinckney, S. Tell, B. Zimmer, T. Raja, K. Zhou, W. Dally, and B. Khailany. ASYNC, page 27-35. IEEE, (2019)Accelerating Chip Design With Machine Learning.B. Khailany, H. Ren, S. Dai, S. Godil, B. Keller, R. Kirby, A. Klinefelter, R. Venkatesan, Y. Zhang, B. Catanzaro and 1 other author(s). IEEE Micro, 40 (6): 23-32 (2020)

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Disambiguation of "Keller, Ben"

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A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI.

Please choose a person to relate this publication to

Ben Koch

Ben Elsner

Ben Abendroth

Ben Weise

Ben Schweizer

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Keller, Ben"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI.

Please choose a person to relate this publication to

Ben Koch

Ben Elsner

Ben Abendroth

Ben Weise

Ben Schweizer

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI.