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Low-cost feedback-enabled LNAs in 45nm CMOS., , , , и . ESSCIRC, стр. 100-103. IEEE, (2009)Identifying the Bottlenecks to the RF Performance of FinFETs., , , , , , и . VLSI Design, стр. 111-116. IEEE Computer Society, (2010)STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process., , , , , , , , и . ESSDERC, стр. 159-162. IEEE, (2013)FinFET technology for analog and RF circuits., , , , , , , и . ICECS, стр. 182-185. IEEE, (2007)Towards high performance sub-10nm finW bulk FinFET technology., , , , , , , , , и 10 other автор(ы). ESSDERC, стр. 131-134. IEEE, (2016)Impact of fin shape variability on device performance towards 10nm node., , , , , , , , , и 3 other автор(ы). ICICDT, стр. 1-4. IEEE, (2015)FinFET RF receiver building blocks operating above 10 GHz., , , , , , , и . ESSCIRC, стр. 360-363. IEEE, (2009)Design Technology co-optimization for N10., , , , , , , , , и 18 other автор(ы). CICC, стр. 1-8. IEEE, (2014)The Potential of FinFETs for Analog and RF Circuit Applications., , , , , , , , , и 5 other автор(ы). IEEE Trans. Circuits Syst. I Regul. Pap., 54-I (11): 2541-2551 (2007)Design issues and considerations for low-cost 3D TSV IC technology., , , , , , , , , и 24 other автор(ы). ISSCC, стр. 148-149. IEEE, (2010)