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Disambiguation of "Chambers, Mark"

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A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling.

, , , , , , , and . IEEE J. Solid State Circuits, 52 (1): 21-32 (2017)

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Helen Chambers

Helen Chambers

Craig Chambers

Mark Yampolsky

Maßnahmen zur Sicherung von E2E-QoS bei verketteten Diensten. Uni München, (2009)

Mark Schütte

Crf2 - ein neues Antigen von Aspergillus fumigatus. TU Braunschweig, (2009)
 

Other publications of authors with the same name

19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC., , , , , , , and . ISSCC, page 324-325. IEEE, (2016)A Low-Power Single-Weight-Combiner 802.11abg SoC in 0.13 µm CMOS for Embedded Applications Utilizing An Area and Power Efficient Cartesian Phase Shifter and Mixer Circuit., , , , , , , , , and 25 other author(s). IEEE J. Solid State Circuits, 43 (5): 1101-1118 (2008)A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling., , , , , , , and . IEEE J. Solid State Circuits, 52 (1): 21-32 (2017)A 2.7GHz to 7GHz fractional-N LCPLL utilizing multimetal layer SoC technology in 28nm CMOS., , , , , , and . VLSIC, page 1-2. IEEE, (2014)A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 50 (4): 856-866 (2015)A PRML read/write channel IC using analog signal processing for 200 Mb/s HDD., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 31 (11): 1817-1830 (1996)Radical wings & wind tunnels: Advanced concepts tested at the NASA Langley, and . Specialty Press, North Branch, MN, (2008)Computed Tomography Radiomics Kinetics as Early Imaging Correlates of Osteoradionecrosis in Oropharyngeal Cancer Patients., , , , , , , , , and 7 other author(s). Frontiers Artif. Intell., (2021)