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X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation., , , , , , , and . AICAS, page 174-177. IEEE, (2022)Modeling of Physical Defects in PN Junction Based Graphene Devices., , , , , and . J. Electron. Test., 30 (3): 357-370 (2014)Analyzing the Impact of SEUs on SRAMs with Resistive-Bridge Defects., , and . VLSID, page 487-492. IEEE Computer Society, (2016)A DfT Strategy for Detecting Emerging Faults in RRAMs., , and . VLSI-SoC (Selected Papers), volume 661 of IFIP Advances in Information and Communication Technology, page 93-111. Springer, (2021)Message from the LATS2015 Chairs., , , and . LATS, page 1. IEEE Computer Society, (2015)Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG., , , , , , , , , and 1 other author(s). LATS, page 1-6. IEEE Computer Society, (2015)SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic., , , , , , and . DDECS, page 223-228. IEEE Computer Society, (2015)Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware., , , , , , and . DAC, page 1-6. IEEE, (2023)