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Другие публикации лиц с тем же именем

Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor., и . NVMSA, стр. 1-6. IEEE, (2017)Delay modeling and static timing analysis for MTCMOS circuits., и . ASP-DAC, стр. 570-575. IEEE, (2006)An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages., , , , и . VLSI-DAT, стр. 1-4. IEEE, (2013)Energy Efficient Approximate Storing of Image Data for MTJ Based Non-Volatile Flip-Flops and MRAM., и . IEICE Trans. Electron., 104-C (7): 338-349 (2021)Geyser-2: The second prototype CPU with fine-grained run-time power gating., , , , , , , , , и 7 other автор(ы). ASP-DAC, стр. 87-88. IEEE, (2011)Overview on Low Power SoC Design Technology.. ASP-DAC, стр. 634-636. IEEE Computer Society, (2007)A fine-grain dynamic sleep control scheme in MIPS R3000., , , , , , , , , и 7 other автор(ы). ICCD, стр. 612-617. IEEE Computer Society, (2008)A 200mV Operable On-Chip Temperature Sensor for IoT Devices Powered by Energy Harvesters with Ultra-Low Output Voltage., , , , и . IoTaIS, стр. 65-71. IEEE, (2023)Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs., , , , , и . NOCS, стр. 61-68. IEEE Computer Society, (2010)Delay Modeling and Critical-Path Delay Calculation for MTCMOS Circuits., и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (12): 3482-3490 (2006)