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Disambiguation of "Pionteck, Thilo"

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Accelerated join evaluation in Semantic Web databases by using FPGAs.

, , , , , and . Concurr. Comput. Pract. Exp., 28 (7): 2031-2051 (2016)

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Thilo Pionteck

Jürgen Pionteck

Uta Thilo

Hans Thilow

Heinz Thilo

 

Other publications of authors with the same name

A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling., and . ISSoC, page 1-6. IEEE, (2014)A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip., , , , and . ReCoSoC, page 1-8. IEEE, (2016)Adaptive allocation of default router paths in Network-on-Chips for latency reduction., , and . HPCS, page 140-147. IEEE, (2016)Continuous live-tracing as debugging approach on FPGAs., , , and . ReConFig, page 1-8. IEEE, (2017)Ratatoskr: An open-source framework for in-depth power, performance and area analysis in 3D NoCs., , , , , and . CoRR, (2019)On the Rapid Prototyping of Equalizers for OFDM Systems., , and . Des. Autom. Embed. Syst., 8 (4): 283-295 (2003)Simulation environment for link energy estimation in networks-on-chip with virtual channels., , , , , and . Integr., (2019)NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures., , , , , , and . IEEE Access, (2019)Design of a reconfigurable AES encryption/decryption engine for mobile terminals., , , , and . ISCAS (2), page 545-548. IEEE, (2004)Integration dynamisch rekonfigurierbarer Funktionseinheiten in Prozessoren., , , , and . ARCS Workshops, volume P-41 of LNI, page 155-164. GI, (2004)