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Continuous live-tracing as debugging approach on FPGAs., , , и . ReConFig, стр. 1-8. IEEE, (2017)A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip., , , , и . ReCoSoC, стр. 1-8. IEEE, (2016)Adaptive allocation of default router paths in Network-on-Chips for latency reduction., , и . HPCS, стр. 140-147. IEEE, (2016)A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling., и . ISSoC, стр. 1-6. IEEE, (2014)Ratatoskr: An open-source framework for in-depth power, performance and area analysis in 3D NoCs., , , , , и . CoRR, (2019)Design of a reconfigurable AES encryption/decryption engine for mobile terminals., , , , и . ISCAS (2), стр. 545-548. IEEE, (2004)Simulation environment for link energy estimation in networks-on-chip with virtual channels., , , , , и . Integr., (2019)NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures., , , , , , и . IEEE Access, (2019)On the Rapid Prototyping of Equalizers for OFDM Systems., , и . Des. Autom. Embed. Syst., 8 (4): 283-295 (2003)Integration dynamisch rekonfigurierbarer Funktionseinheiten in Prozessoren., , , , и . ARCS Workshops, том P-41 из LNI, стр. 155-164. GI, (2004)