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Disambiguation of "Pontes, Julian J. H."

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Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques.

, , , and . ISVLSI, page 347-352. IEEE Computer Society, (2008)

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Julian H Sprau

Julian J Zemke

H J Plüss

H -J Bielig

J. H. Merkin

 

Other publications of authors with the same name

Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects., , and . ASYNC, page 142-149. IEEE Computer Society, (2012)Hermes-A - An Asynchronous NoC Router with Distributed Routing., , , and . PATMOS, volume 6448 of Lecture Notes in Computer Science, page 150-159. Springer, (2010)Soft error mitigation in asynchronous networks on chip.. Pontifícia Universidade Católica do Rio Grande do Sul, Porto Alegre, Brazil, (2012)ndltd.org (oai:tede2.pucrs.br:tede/5198).A 65nm standard cell set and flow dedicated to automated asynchronous circuits design., , , and . SoCC, page 99-104. IEEE, (2011)Adapting a C-element design flow for low power., , , , and . ICECS, page 45-48. IEEE, (2011)SCAFFI: An intrachip FPGA asynchronous interface based on hard macros., , , , and . ICCD, page 541-546. IEEE, (2007)Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques., , , and . ISVLSI, page 347-352. IEEE Computer Society, (2008)Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design., , and . ISQED, page 692-699. IEEE, (2014)2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters., , , , , , , , , and 18 other author(s). ISSCC, page 46-48. IEEE, (2020)H2A: A hardened asynchronous network on chip., , and . SBCCI, page 1-6. IEEE, (2013)