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Temporal and System Level Modifications for High Speed VLSI Implementations of Cryptographic Core., , , , , and . ICECS, page 1180-1183. IEEE, (2006)A survey for UAV open-source telemetry protocols., , , , and . PCI, page 346-351. ACM, (2021)A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000., , , and . Integr., 39 (1): 1-11 (2005)Low-power architecture with scratch-pad memory for accelerating embedded applications with run-time reuse., , , , , , and . IET Comput. Digit. Tech., 3 (1): 109-123 (2009)A Low Power Design for Sbox Cryptographic Primitive of Advanced Encryption Standard for Mobile End-Users., , , , and . J. Low Power Electron., 3 (3): 327-336 (2007)Architecture for Secure UAV Systems., , and . PCI, page 99-102. ACM, (2020)A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms., , , , and . DATE, page 247-252. IEEE Computer Society, (2004)Arithmetic module-based built-in self test architecture for two-pattern testing., , , and . IET Comput. Digit. Tech., 6 (4): 195-204 (2012)Automated framework for partitioning DSP applications in hybrid reconfigurable platforms., , , , and . Microprocess. Microsystems, 31 (1): 1-14 (2007)High-Speed FPGA Implementation of Secure Hash Algorithm for IPSec and VPN Applications., , , , and . J. Supercomput., 37 (2): 179-195 (2006)