( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS.

, , , , , , , , , , , , , , , , и . ISSCC, стр. 64-65. IEEE, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Kano Banjau

Eitoku Kano

Hideki Teshima

Hideki Mine

Hideki Nakamura

 

Другие публикации лиц с тем же именем

A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets., , , , , , , , , и 10 other автор(ы). ISSCC, стр. 86-88. IEEE, (2012)3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS., , , , , , , , , и 7 other автор(ы). ISSCC, стр. 64-65. IEEE, (2016)A 28-Gb/s 4.5-pJ/bit transceiver with 1-tap decision feedback equalizer in 28-nm CMOS., , , , , , , , , и 3 other автор(ы). A-SSCC, стр. 1-4. IEEE, (2015)A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE., , , , , , , , , и 4 other автор(ы). IEEE J. Solid State Circuits, 49 (12): 2915-2924 (2014)3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE., , , , , , , , , и 5 other автор(ы). ISSCC, стр. 60-61. IEEE, (2014)A 1-Gb SDRAM with ground-level precharged bit line and nonboosted 2.1-V word line., , , , , , , , , и 6 other автор(ы). IEEE J. Solid State Circuits, 33 (11): 1697-1702 (1998)A 43-Gb/s full-rate-clock 4: 1 multiplexer in InP-based HEMT technology., , , , , , , , , и 2 other автор(ы). IEEE J. Solid State Circuits, 37 (12): 1703-1709 (2002)A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS., , , , , , , , , и 10 other автор(ы). VLSI Circuits, стр. 1-2. IEEE, (2016)