( en | de | ru )

 

Disambiguation of "Tu, Ming-Hsien"

Author of the publication

copydeleteadd this publication to your clipboard
Testing strategies for a 9T sub-threshold SRAM.

, , , , , , and . ITC, page 1-10. IEEE Computer Society, (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Ming-Hsien Wong

Jun-Ming Tu

Yi-Ming Tu

Linda Hsien

Shiwei Tu

 

Other publications of authors with the same name

A 0.35 V, 375 kHz, 5.43 µW, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line., , , , , , and . Microelectron. J., (2016)40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (9): 2578-2585 (2014)Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (12): 3039-3047 (2010)Testing strategies for a 9T sub-threshold SRAM., , , , , , and . ITC, page 1-10. IEEE Computer Society, (2012)A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist., , , , , , , , , and 9 other author(s). ISCAS, page 1468-1471. IEEE, (2013)8T single-ended sub-threshold SRAM with cross-point data-aware write operation., , , , and . ISLPED, page 169-174. IEEE/ACM, (2011)A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control., , , , , , , , , and 3 other author(s). SoCC, page 110-115. IEEE, (2013)A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist., , , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (5): 958-962 (2015)A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist., , , , , and . ISLPED, page 51-56. IEEE, (2013)A reconfigurable MAC architecture implemented with mixed-Vt standard cell library., , , , , and . ISCAS, page 3426-3429. IEEE, (2008)