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Full-digital high throughput design of adaptive decision feedback equalizers using coefficient-lookahead., , , and . ASICON, page 1-4. IEEE, (2015)A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control., , , , , , , , , and 9 other author(s). SoCC, page 197-200. IEEE, (2011)Power and area reduction in multi-stage addition using operand segmentation., , , and . VLSI-DAT, page 1-4. IEEE, (2013)An ultra-low voltage hearing aid chip using variable-latency design technique., , , , , and . ISCAS, page 2543-2546. IEEE, (2014)An embedded DSP core for wireless communication., , , , and . ISCAS (4), page 524-527. IEEE, (2002)4/2 PAM serial link transmitter with tunable pre-emphasis., , , and . ISCAS (1), page 952-958. IEEE, (2004)A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology., , , , , and . SoCC, page 160-164. IEEE, (2014)A 12.5 Gbps CMOS input sampler for serial link receiver front end., , and . ISCAS (2), page 1055-1058. IEEE, (2005)Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (12): 3039-3047 (2010)A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (3): 743-751 (2015)