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Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing., , и . ACM Trans. Design Autom. Electr. Syst., 17 (2): 18:1-18:24 (2012)A Novel ATPG Method for Capture Power Reduction during Scan Testing., , , , , , и . IEICE Trans. Inf. Syst., 90-D (9): 1398-1405 (2007)Self-Testing of Embedded RAMs., и . ITC, стр. 148-156. IEEE Computer Society, (1984)Turbo1500: Core-Based Design for Test and Diagnosis., , , , , , , , , и 5 other автор(ы). IEEE Des. Test Comput., 26 (1): 26-35 (2009)Low-capture-power test generation for scan-based at-speed testing., , , , , , и . ITC, стр. 10. IEEE Computer Society, (2005)At-Speed Logic BIST for IP Cores., , , , , , , , и . DATE, стр. 860-861. IEEE Computer Society, (2005)CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing., , , , , , , и . ATS, стр. 397-402. IEEE Computer Society, (2008)GPU-based timing-aware test generation for small delay defects., , , , , и . ETS, стр. 1-2. IEEE, (2014)Luncheon Speaker: "Introduction to SoC testing".. SoCC, стр. 256-257. IEEE, (2011)Condensed Linear Feedback Shift Register (LFSR) Testing - A Pseudoexhaustive Test Technique., и . IEEE Trans. Computers, 35 (4): 367-370 (1986)