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Disambiguation of "Sakuma, Katsuyuki"

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Chip-level TSV integration for rapid prototyping of 3D system LSIs.

, , , , , , , , and . 3DIC, page 1-4. IEEE, (2011)

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Hidenori Sakuma

Hironobu Sakuma

Yasuhiko Sakuma

Yasuhiko Sakuma

 

Other publications of authors with the same name

Thermal design guideline and new cooling solution for a three-dimensional (3D) chip stack., , , , , , , , , and 1 other author(s). 3DIC, page 1-8. IEEE, (2013)Thermal stress analysis of die stacks with fine-pitch IMC interconnections for 3D integration., , , , , , , , and . 3DIC, page 1-7. IEEE, (2011)Three-dimensional silicon integration., , , , , , , , , and 6 other author(s). IBM J. Res. Dev., 52 (6): 553-569 (2008)Thermal resistance measurements of interconnections for a three-dimensional (3D) chip stack., , , and . 3DIC, page 1-5. IEEE, (2009)Turning the Finger into a Writing Tool., , , , and . EMBC, page 1239-1242. IEEE, (2019)3D chip stacking with C4 technology., , , , , , , , , and 4 other author(s). IBM J. Res. Dev., 52 (6): 599-609 (2008)Chip-level TSV integration for rapid prototyping of 3D system LSIs., , , , , , , , and . 3DIC, page 1-4. IEEE, (2011)10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack., , , , , , , , , and . 3DIC, page 1-6. IEEE, (2009)Future system-on-silicon LSI chips., , , , , and . IEEE Micro, 18 (4): 17-22 (1998)High density 3D integration by pre-applied Inter Chip Fill., , , , , , , , and . 3DIC, page 1-5. IEEE, (2010)