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Disambiguation of "Hosokawa, Toshinori"

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Design for testability using register-transfer level partial scan selection.

, , , , , , and . ASP-DAC, ACM, (1995)

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Toshinori Kuwahara

Kōmei Hosokawa

Hirofumi Hosokawa

Roberto Tuyoshi Hosokawa

 

Other publications of authors with the same name

A DFT Selection Method for Reducing Test Application Time of System-on-Chips., , , , and . IEICE Trans. Inf. Syst., 87-D (3): 609-619 (2004)A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint., , and . IEICE Trans. Inf. Syst., 93-D (1): 24-32 (2010)A Test Sensitization State Compaction Method on Controller Augmentation., , , and . IOLTS, page 1-6. IEEE, (2020)CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer Level., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 107 (3): 583-591 (2024)Universal Testing for Linear Feed-Forward/Feedback Shift Registers., , and . IEICE Trans. Inf. Syst., 103-D (5): 1023-1030 (2020)A State Assignment Method to Improve Transition Fault Coverage for Controllers., , , and . DFT, page 1-4. IEEE, (2019)Test sequence compaction methods for acyclic sequential circuits using a time expansion model., , , and . Syst. Comput. Jpn., 33 (10): 105-115 (2002)A Hardware Trojan Circuit Detection Method Using Activation Sequence Generations., , and . PRDC, page 221-222. IEEE Computer Society, (2017)A Test Point Insertion Method to Reduce the Number of Test Patterns., , and . Asian Test Symposium, page 298-304. IEEE Computer Society, (2002)A Test Generation Method for Data Paths Using Easily Testable Functional Time Expansion Models and Controller Augmentation., , , and . ATS, page 37-42. IEEE Computer Society, (2015)