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A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation., , , , , , , , , and 10 other author(s). IEEE J. Solid State Circuits, 50 (1): 178-190 (2015)A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 55 (1): 157-166 (2020)13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process., , , , , , , , , and 27 other author(s). ISSCC, page 234-236. IEEE, (2024)13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration., , , , , , , , , and 25 other author(s). ISSCC, page 242-244. IEEE, (2024)25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation., , , , , , , , , and 16 other author(s). ISSCC, page 430-431. IEEE, (2014)A Digital PLL with 5-Phase Digital PFD for Low Long-term Jitter Clock Recovery., , , , and . CICC, page 745-748. IEEE, (2006)A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus., , , , , , , , , and 24 other author(s). ISSCC, page 446-448. IEEE, (2022)AC Analysis of Thin Gate Oxide MOS with Quantum Mechanical Corrections., , and . ISQED, page 326-330. IEEE Computer Society, (2002)A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction., , , , , , , , , and 20 other author(s). IEEE J. Solid State Circuits, 46 (1): 107-118 (2011)23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme., , , , , , , , , and 27 other author(s). ISSCC, page 390-391. IEEE, (2017)