Author of the publication

pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction.

T. Oh, Y. Sohn, S. Bae, M. Park, J. Lim, Y. Cho, D. Kim, D. Kim, H. Kim, H. Kim, J. Kim, J. Kim, Y. Kim, B. Kim, S. Kwak, J. Lee, J. Lee, C. Shin, Y. Yang, B. Cho, S. Bang, H. Yang, Y. Choi, G. Moon, C. Park, S. Hwang, J. Lim, K. Park, J. Choi, and Y. Jun. IEEE J. Solid State Circuits, 46 (1): 107-118 (2011)

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Jeong-Taeg Lim

Jeong-Sun Lim

Don Lamb

Don Yoon

Su-Jeong Jeong

Other publications of authors with the same name

A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process.D. Kim, B. Song, H. Ahn, W. Ko, S. Do, S. Cho, K. Kim, S. Oh, H. Joo, G. Park and 37 other author(s). ISSCC, page 448-450. IEEE, (2022)A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput.S. Lee, C. Kim, M. Kim, S. Joe, J. Jang, S. Kim, K. Lee, J. Kim, J. Park, H. Lee and 32 other author(s). ISSCC, page 340-342. IEEE, (2018)A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction.T. Oh, Y. Sohn, S. Bae, M. Park, J. Lim, Y. Cho, D. Kim, D. Kim, H. Kim, H. Kim and 20 other author(s). IEEE J. Solid State Circuits, 46 (1): 107-118 (2011)A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW.S. Bae, Y. Sohn, T. Oh, S. Kim, Y. Yang, D. Kim, S. Kwak, H. Seol, C. Shin, M. Park and 19 other author(s). ISSCC, page 498-500. IEEE, (2011)7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip.H. Kim, J. Lim, J. Lee, D. Na, J. Shin, C. Kim, S. Yu, J. Shin, S. Lee, D. Rajagopal and 20 other author(s). ISSCC, page 1-3. IEEE, (2015)13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate.D. Kim, H. Kim, S. Yun, Y. Song, J. Kim, S. Joe, K. Kang, J. Jang, H. Yoon, K. Lee and 35 other author(s). ISSCC, page 218-220. IEEE, (2020)A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction.T. Oh, Y. Sohn, S. Bae, M. Park, J. Lim, Y. Cho, D. Kim, D. Kim, H. Kim, H. Kim and 20 other author(s). ISSCC, page 434-435. IEEE, (2010)

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Disambiguation of "Lim, Jeong-Don"

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A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction.

Please choose a person to relate this publication to

Jeong-Taeg Lim

Jeong-Sun Lim

Don Lamb

Don Yoon

Su-Jeong Jeong

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lim, Jeong-Don"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction.

Please choose a person to relate this publication to

Jeong-Taeg Lim

Jeong-Sun Lim

Don Lamb

Don Yoon

Su-Jeong Jeong

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction.