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Disambiguation of "Yang, Hyang-Ja"

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A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction.

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Yeung Ja Yang

Ja-Yang Park

Yang Yang

Yang Yang

Yang Yang

 

Other publications of authors with the same name

19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming., , , , , , , , , and 35 other author(s). ISSCC, page 334-335. IEEE, (2014)A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques., , , , , , , , , and 16 other author(s). ISSCC, page 278-279. IEEE, (2008)7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate., , , , , , , , , and 24 other author(s). ISSCC, page 1-3. IEEE, (2015)A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction., , , , , , , , , and 20 other author(s). ISSCC, page 434-435. IEEE, (2010)A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction., , , , , , , , , and 20 other author(s). IEEE J. Solid State Circuits, 46 (1): 107-118 (2011)A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW., , , , , , , , , and 19 other author(s). ISSCC, page 498-500. IEEE, (2011)7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip., , , , , , , , , and 20 other author(s). ISSCC, page 1-3. IEEE, (2015)7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers., , , , , , , , , and 20 other author(s). ISSCC, page 130-131. IEEE, (2016)7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate., , , , , , , , , and 35 other author(s). ISSCC, page 138-139. IEEE, (2016)A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate., , , , , , , , , and 19 other author(s). IEEE J. Solid State Circuits, 51 (1): 204-212 (2016)