Author of the publication

pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction.

T. Oh, Y. Sohn, S. Bae, M. Park, J. Lim, Y. Cho, D. Kim, D. Kim, H. Kim, H. Kim, J. Kim, J. Kim, Y. Kim, B. Kim, S. Kwak, J. Lee, J. Lee, C. Shin, Y. Yang, B. Cho, S. Bang, H. Yang, Y. Choi, G. Moon, C. Park, S. Hwang, J. Lim, K. Park, J. Choi, and Y. Jun. IEEE J. Solid State Circuits, 46 (1): 107-118 (2011)

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Kwang Park

Sun-Kwang Park

Kwang Woo Park

Kwang-jack Park

Kwang-Ki Park

Other publications of authors with the same name

A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration.J. Heo, K. Kim, D. Lee, C. Lee, D. Moon, K. Kim, J. Baek, S. Yoon, H. Yang, K. Kim and 14 other author(s). VLSI Circuits, page 114-. IEEE, (2019)HMM and Rule-Based Hybrid Intruder Detection Approach by Synthesizing Decisions of Sensors.K. Kim, K. Park, Y. Jeong, J. Hong, H. Kim, and W. Kim. Int. J. Distributed Sens. Networks, (2013)A Wormhole Router with Embedded Broadcasting Virtual Bus for Mesh Computers.B. Kim, J. Choi, K. Park, and K. Park. Parallel Process. Lett., 10 (1): 29-37 (2000)A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces.B. Kim, L. Kim, K. Park, Y. Jun, and S. Cho. IEEE J. Solid State Circuits, 44 (5): 1522-1530 (2009)A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation.T. Oh, H. Chung, J. Park, K. Lee, S. Oh, S. Doo, H. Kim, C. Lee, H. Kim, J. Lee and 10 other author(s). IEEE J. Solid State Circuits, 50 (1): 178-190 (2015)A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme.K. Oh, L. Kim, K. Park, Y. Jun, J. Choi, and K. Kim. IEEE J. Solid State Circuits, 44 (8): 2222-2232 (2009)A Methodology Combining Cosine Similarity with Classifier for Text Classification.K. Park, J. Hong, and W. Kim. Applied Artificial Intelligence, 34 (5): 396-411 (2020)A DLL with Jitter-Reduction Techniques for DRAM Interfaces.B. Kim, L. Kim, K. Park, Y. Jun, and S. Cho. ISSCC, page 496-497. IEEE, (2007)Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond.J. Kim, S. Kang, S. Lee, H. Kim, W. Song, Y. Ro, S. Lee, D. Wang, H. Shin, B. Phuah and 10 other author(s). HCS, page 1-26. IEEE, (2021)Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM.Y. Peng, B. Ku, Y. Park, K. Park, S. Jang, J. Choi, and S. Lim. DAC, page 91:1-91:6. ACM, (2015)

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Disambiguation of "Park, Kwang-Il"

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A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction.

Please choose a person to relate this publication to

Kwang Park

Sun-Kwang Park

Kwang Woo Park

Kwang-jack Park

Kwang-Ki Park

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Park, Kwang-Il"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction.

Please choose a person to relate this publication to

Kwang Park

Sun-Kwang Park

Kwang Woo Park

Kwang-jack Park

Kwang-Ki Park

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction.