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A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications.

K. Siozios, D. Soudris, and A. Thanailakis. ISCAS, IEEE, (2006)

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Dimitrios Karantonis

Dimitrios Koulousakis

Dimitrios Repantis

Dimitrios Parashu

Dimitrios Papasotiriou

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Understanding timing impact of BTI/RTN with massively threaded atomistic transient simulations.D. Rodopoulos, D. Stamoulis, G. Lyras, D. Soudris, and F. Catthoor. ICICDT, page 1-4. IEEE, (2014)On the implementation of a baseband processor for a portable dual mode DECT/GSM terminal.C. Drosos, C. Dre, S. Blionas, and D. Soudris. ISCAS (4), page 334-337. IEEE, (2001)Accuracy of Quasi-Monte Carlo technique in failure probability estimations.M. Noltsis, P. Weckx, D. Rodopoulos, F. Catthoor, and D. Soudris. ICICDT, page 1-4. IEEE, (2016)A reusable IP FFT core for DSP applications.E. Theochari, K. Tatas, D. Soudris, K. Masselos, K. Potamianos, S. Blionas, and A. Thanailakis. ISCAS (3), page 621-624. IEEE, (2004)A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications.K. Siozios, D. Soudris, and A. Thanailakis. ISCAS, IEEE, (2006)Distributed run-time resource management for malleable applications on many-core platforms.I. Anagnostopoulos, V. Tsoutsouras, A. Bartzas, and D. Soudris. DAC, page 168:1-168:6. ACM, (2013)Designing Heterogeneous FPGAs with Multiple SBs.K. Siozios, S. Mamagkakis, D. Soudris, and A. Thanailakis. ARC, volume 4419 of Lecture Notes in Computer Science, page 91-96. Springer, (2007)A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck.M. Dasygenis, E. Brockmeyer, B. Durinck, F. Catthoor, D. Soudris, and A. Thanailakis. IEEE Trans. Very Large Scale Integr. Syst., 14 (3): 279-291 (2006)DDOT: Data Driven Online Tuning for energy efficient acceleration.S. Xydis, E. Christoforidis, and D. Soudris. DAC, page 1-6. IEEE, (2020)GPU accelerated blockchain over key-value database transactions.K. Iliakis, K. Koliogeorgi, A. Litke, T. Varvarigou, and D. Soudris. IET Blockchain, 2 (1): 1-12 (2022)

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Disambiguation of "Soudris, Dimitrios"

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A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications.

Please choose a person to relate this publication to

Dimitrios Karantonis

Dimitrios Koulousakis

Dimitrios Repantis

Dimitrios Parashu

Dimitrios Papasotiriou

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Soudris, Dimitrios"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications.

Please choose a person to relate this publication to

Dimitrios Karantonis

Dimitrios Koulousakis

Dimitrios Repantis

Dimitrios Parashu

Dimitrios Papasotiriou

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications.