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Disambiguation of "Alizadeh, Bijan"

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Low power scheduling in high-level synthesis using dual-Vth library.

, , and . ISQED, page 507-511. IEEE, (2015)

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Jasmin Bijani

Khosrow Alizadeh

Alireza Alizadeh

Mansour Alizadeh

Hüssein Alizadeh

 

Other publications of authors with the same name

Systematic approximate logic optimization using don't care conditions., , , and . ISQED, page 419-425. IEEE, (2017)Debugging and optimizing high performance superscalar out-of-order processors using formal verification techniques., and . ISQED, page 297-302. IEEE, (2011)Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only)., , and . FPGA, page 288. ACM, (2010)High-Level Synthesis of Non-Rectangular Multi-Dimensional Nested Loops Using Reshaping and Vectorization., , and . ICRC, page 1-10. IEEE, (2018)Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions., and . ATVA, volume 4762 of Lecture Notes in Computer Science, page 129-144. Springer, (2007)Systematic Trojan Detection in Crypto-Systems Using the Model Checker., , and . J. Circuits Syst. Comput., (February 2024)A formal approach to debug polynomial datapath designs.. ASP-DAC, page 683-688. IEEE, (2012)Modular arithmetic decision procedure with auto-correction mechanism., and . HLDVT, page 138-145. IEEE Computer Society, (2009)Highly scalable, shared-memory, Monte-Carlo tree search based Blokus Duo Solver on FPGA., , , , , , and . FPT, page 370-373. IEEE, (2014)UAFEA: Unified Analytical Framework for IA/AA-Based Error Analysis of Fixed-Point Polynomial Specifications., , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (10): 994-998 (2016)